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configurable, high g, i mems accelerometer adxl180 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008 analog devices, inc. all rights reserved. features wide sensor range: 50 g to 500 g adjustable filter bandwidth: 100 hz to 800 hz configurable communication protocol 2-wire, current mode bus interface selectable sensor data resolution: 8 bit or 10 bit continuous auto-zero fully differential sensor and interface circuitry high resistance to emi/rfi sensor self-test 5.0 v to 14.5 v operation 8 bits of user-defined otp memory 32-bit electronic serial number dual device per bus option applications crash sensing general description the adxl180 i mems? accelerometer is a configurable, single axis, integrated satellite sensor that enables low cost solutions for front and side impact airbag applications. acceleration data is sent to the control module via a digital 2-wire current loop interface bus. the communication protocol is programmable for compatibility with various automotive interface bus standards. the sensor g range is configurable to provide full-scale ranges from 50 g to 500 g . the sensor signal third-order, low-pass bessel filter bandwidth is configurable at 100 hz, 200 hz, 400 hz, and 800 hz. the 10-bit analog-to-digital converter (adc) allows either 8-bit or 10-bit acceleration data to be transmitted to the control module. each part has a unique electronic serial number. the device is rated for operation from ?40c to +125c and is available in a 5 mm 5 mm lfcsp package. functional block diagram v bn v dd adxl180 v bp 3-pole bessel filter trims 10- bit adc voltage regulator comm interface serial port state machine serial number supply monitor auto- zero sync detect program interface configuration data otp fuse rom v bc self- test 07544-001 diff sensor mod oscillator/ timing generator demod amp v cm ref v sco v cm v/q v sci figure 1.
adxl180 rev. a | page 2 of 60 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications ..................................................................................... 4 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? terminology ...................................................................................... 9 ? theory of operation ...................................................................... 10 ? overview ...................................................................................... 10 ? acceleration sensor .................................................................... 10 ? signal processing ........................................................................ 11 ? digital communications state machine ................................. 11 ? 2-wire current modulated interface ....................................... 11 ? synchronous operation and dual device bus ....................... 11 ? programmed memory and configurability ............................ 11 ? physical interface ............................................................................ 13 ? application circuit ..................................................................... 13 ? current modulation ................................................................... 13 ? manchester data encoding ....................................................... 14 ? operation at low v bp or low v dd ............................................ 14 ? operation at high v dd ............................................................... 14 ? communications timing and bus topologies ........................... 15 ? data transmission ...................................................................... 15 ? asynchronous communication ............................................... 16 ? synchronous communication .................................................. 17 ? synchronous communication modedual device ............. 19 ? data frame definition ................................................................... 23 ? data frame transmission format ............................................ 23 ? data frame configuration options ......................................... 23 ? acceleration data coding ......................................................... 25 ? state vector coding ................................................................... 26 ? state vector descriptions .......................................................... 26 ? transmission error detection options ................................... 27 ? application layer: communication protocol state machine ... 28 ? adxl180 state machine ........................................................... 28 ? phase 1: power-on-reset initialization .................................... 28 ? phase 2: device data transmission ......................................... 28 ? phase 2: mode description ....................................................... 30 ? phase 3: self-test diagnostic .................................................... 37 ? phase 4: auto-zero initialization ............................................. 40 ? phase 5: normal operation ...................................................... 40 ? signal range and filtering ............................................................ 41 ? transfer function overview ..................................................... 41 ? range ............................................................................................ 41 ? three-pole bessel filter ............................................................. 41 ? auto-zero operation ................................................................. 41 ? error detection ............................................................................... 43 ? overview ..................................................................................... 43 ? parity error due to communications protocol configuration bit error ....................................................................................... 43 ? self-test error ............................................................................. 44 ? offset error/offset drift monitoring ...................................... 44 ? voltage regulator monitor reset operation .......................... 44 ? test and diagnostic tools ............................................................. 45 ? v sci signal chain input test pin .............................................. 45 ? v sco analog signal chain output test pin ............................ 45 ? configuration specification .......................................................... 46 ? overview ..................................................................................... 46 ? configuration mode transmit communications protocol .. 47 ? configuration mode command (receive) communications protocol........................................................................................ 48 ? configuration mode communications handshaking .......... 49 ? configuration and user data registers .................................. 50 ? configuration mode exit .......................................................... 50 ? serial number and manufacturer identification data registers ....................................................................................... 50 ? programming the configuration and user data registers .. 50 ? otp programming conditions and considerations ............ 51 ? configuration/user register otp parity ................................ 51 ? configuration mode error reporting ..................................... 51 ? configuration register reference ................................................ 52 ? ud[7:0] user data bits .............................................................. 53 ? ud8 configuration bit .............................................................. 53 ? bde .............................................................................................. 53 ? scoe ............................................................................................ 53 ? fdly ............................................................................................ 53 ? adme .......................................................................................... 53 ? sti ................................................................................................ 53 ?
adxl180 rev. a | page 3 of 60 fc[1:0] .......................................................................................... 53 ? rg[2:0] ......................................................................................... 53 ? md[1:0] ........................................................................................ 54 ? syen ............................................................................................. 55 ? aze ............................................................................................... 55 ? erc ............................................................................................... 55 ? dat ............................................................................................... 55 ? svd ............................................................................................... 55 ? cupar and cuprg .................................................................. 55 ? axis of sensitivity ............................................................................ 56 ? branding ........................................................................................... 57 ? outline dimensions ........................................................................ 58 ? ordering guide ........................................................................... 58 ? revision history 11/08rev. 0 to rev. a added data transmission section ................................................ 15 added new figure 10, renumbered sequentially ...................... 15 added new figure 11 ..................................................................... 16 changes to figure 14 ...................................................................... 18 changes to figure 16 ...................................................................... 20 changes to synchronization pulse detection section ............... 17 8/08revision 0: initial version
adxl180 rev. a | page 4 of 60 specifications t a = ?40c to +125c, v bp ? v bn = 5.0 v to 14.5 v, f lp = 400 hz, acceleration = 0 g , unless otherwise noted. table 1. parameter 1 symbol min typ max unit test conditions/comments sensor scale factor measurement frequency: 100 hz 50 g range see table 37 8-bit data 0.465 0.50 0.535 g /lsb 10-bit data 0.116 0.1250 0.134 g /lsb 100 g range 8-bit data 0.930 1.00 1.070 g /lsb 10-bit data 0.233 0.2500 0.268 g /lsb 150 g range 8-bit data 1.395 1.50 1.605 g /lsb 10-bit data 0.349 0.3750 0.401 g /lsb 200 g range 8-bit data 1.860 2.00 2.140 g /lsb 10-bit data 0.465 0.5000 0.535 g /lsb 250 g range 8-bit data 2.325 2.50 2.675 g /lsb 10-bit data 0.581 0.625 0.669 g /lsb 350 g range 8-bit data 3.255 3.50 3.745 g /lsb 10-bit data 0.830 0.8925 0.955 g /lsb 500 g range 8-bit data 4.650 5.00 5.350 g /lsb 10-bit data 1.163 1.2500 1.338 g /lsb offset all ranges, auto-zero disabled 8-bit data ?12 +11 lsb 10-bit data ?48 +47 lsb noise (peak-to-peak) 50 g range 8-bit data 2 lsb 10 hz to 400 hz 10-bit data 2 3 lsb 10 hz to 400 hz self test amplitude 20 25 30 g internal self-test limit 20 30 g sti enabled, see table 35 nonlinearity 0.2 2 % of full-scale range cross-axis sensitivity ?5 +5 % resonant frequency 12.8 khz q 1.5 low-pass filter frequency response third-order bessel pass band f lp programmable, see table 38 ?3 db frequency 670 800 880 hz ?3 db frequency 335 400 440 hz ?3 db frequency 167.5 200 220 hz ?3 db frequency 83.75 100 110 hz auto-zero update rate slow mode 5.0 sec/lsb 10-bit lsb fast mode 0.5 sec/lsb 10-bit lsb
adxl180 rev. a | page 5 of 60 parameter 1 symbol min typ max unit test conditions/comments regulator voltage monitor regulator operating voltage v dd 4.20 v power-up reset voltage v pur 3.77 4.0 4.23 v see figure 33 overvoltage level v ov 4.7 4.95 5.3 v see figure 33 reset hysteresis voltage v hyst 0.12 v communications interface quiescent (idle) current i ldle 5 6 7.7 ma modulation current i mod 23 25 30 ma signal current i sig 28 31 37.7 ma i sig = i idle + i mod autodelay detect current i det 18 22 26 ma total including i idle data bit period 2 t b 8 s t b = 8 t clk data bit duty cycle d dc 45 50 53 % d dc = t a /t b , see figure 7 data bit rise/fall see figure 7 fall time t r 400 1000 ns rise time t f 350 1000 ns encoding manchester see figure 8 adc conversion time 2 t adc 35 s see figure 12 error checking (selectable) number of crc bits 3 x3 + x1+ x 0 number of parity bits 1 even synchronization pulse detect no detect limit v spnd 3.0 v detect threshold v spt 3.5 v v bp ? v bn + v spt 14.5 v; see figure 14 threshold hysteresis 0.1 v synchronization pulse detect time t spd 8 t clk see figure 14 synchronization pulse discharge (pull-down) time t spp 40 t clk see figure 14 synchronization mode transmission delay t std 63 t clk see figure 14 configuration mode receive communications interface all @ 25c only; v bp ? v bn + v ct 12.25 v detect threshold v ct 5.25 v see figure 35 threshold hysteresis 0.1 v interbit time t ib 250 t clk see figure 35 data 0 pulse width t pg0 40 55 t clk see figure 35 data 1 pulse width t pg1 80 t clk see figure 35 configuration mode response time t tm1 24 s see figure 35 configuration mode write delay time t tm2 50 s see figure 35 v bp during fuse programming v bpf 7.5 v compliant up to the maximum operating voltage v bp current during fuse programming i fp 15 ma maximum drawn by the part
adxl180 rev. a | page 6 of 60 parameter 1 symbol min typ max unit test conditions/comments asynchronous mode timing 2 message transmission period phase 2, mode 0 t pm0 456 s adifx compatible all other phases and modes t p 228 s initialization state (phase 1) t i 100 ms device data state (phase 2) ms mode 0 t dd0 4.10 ms mode 1 t dd1 109 ms mode 2 t dd2 109 ms mode 3 t dd3 117 ms self-test state (phase 3) self-test time 3 t st 394 ms see figure 28 self-test interval t sti 21.9 ms see figure 28 self-test cycle t stc 65.7 ms see figure 28 auto-zero initialization state (phase 4) t az 14.94 sec synchronous mode timing 4 message transmission period t ps n/a determined by sync pulse, see figure 14 , minimum t ps = t spd + t std + t m + t b initialization state1 (phase 1) t i 100 ms device data state (phase 2) ms mode 0 t dd0s 9 t ps ms mode 1 t dd1s 480 t ps ms mode 2 t dd2s 480 t ps ms mode 3 t dd3s 512 t ps ms self-test state (phase 3) self-test time 3 t sts 1728 t ps ms self-test interval t stis 96 t ps ms self-test cycle t stcs 288 t ps ms auto-zero initialization state (phase 4) t azs 65,535 t ps sec clock period 2 t clk 1.05 1.0 0.95 s f clk = 1/t clk psrr <1 lsb 8-bit lsb; test conditions: v bp ? v bn = 7.00 v, v ac = 500 mv p-p, 100 khz to 1.1 mhz power supply holdup time 500 ns @ i bus = i sig thermal resistance, junction to case jc 30 c/w 1 all parameters are specif ied using the application circuit shown in figure 6. c b = 10 nf, c vdd = 100 nf. 2 all timing is driven from the on-chip master clock. 3 t st and t sts are the times for six self-test cycles. this is the maximum number of cycles in the internal self-test mode. 4 transmission timing is defined by the internal system clock in asynchronous mode and by the sy nchronization pulse period in sy nchronous mode.
adxl180 rev. a | page 7 of 60 absolute maximum ratings table 2. parameter rating supply voltage (v bp ? v bn ) ?0.3 v to +21 v voltage at any pin with respect to v bn except v bp ?0.3 v to v dd + 0.3 v storage temperature range ?55c to +150c soldering temperature 255c operating temperature range ?40c to +125c esd all pins 1.5 kv hbm latch-up current 100 ma mechanical shock unpowered 4000 g (0.5 ms, half sine) powered 2000 g (0.5 ms, half sine); ?0.3 v to +7.0 v drop test (onto concrete) 1 1.2 m thermal gradient 20c/minute 1 soldered to fr4 coupon printed circuit board (pcb) at the dimensions of 25.4 mm 25 mm. during test, the pcb is fastened to a support with 46 g mass, equivalent to a typical satellite module pcb. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution ramp-down ramp-up critical zone t l to t p temperature t a = 25c t l t p time t = 25c to peak t s preheat t l t p t smin t smax 07544-002 figure 2. adxl180 pb-free solder profile table 3. adxl solder profile parameters profile feature small body pb-free assemblies average ramp-up rate (t l to t p ) 3c/second maximum preheat temperature min (t s min) to temperature max (t s max) 150c to 200c time (min to max) (t s ) 60 sec to 180 sec t s max to t l ramp-up rate 3c/second maximum time maintained above temperature (t l ) 217c time (t l ) 60 sec to 150 sec peak temperature (t p ) 260c +5/?5c time within 5c of actual peak temperature (t p ) 20 sec to 40 sec ramp-down rate 6c/sec maximum time 25c to peak temperature 8 minutes maximum
adxl180 rev. a | page 8 of 60 pin configuration and fu nction descriptions v dd nc v sco v cm v cm v bp v bn v bc nc nc nc 9 10 11 12 v bn v cm 13 14 15 16 v cm nc v sci 4 3 2 1 8 7 6 v bn 5 v bn nc = no connect dap1 adxl180 top view (not to scale) dap2 07544-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 nc reserved for analog devices, inc., use only. v bn or do not connect. 2 v cm reserved for analog devices use only. do not connect. 3 v bn negative bus voltage. 4 nc reserved for analog devices use only. v bn or do not connect. 5 v dd voltage regulator bypass capacitor. 6 nc reserved for analog devices use only. v bn or do not connect. 7 v sco reserved for analog devices use only. do not connect. 8 v bn negative bus voltage. 9 v bc daisy-chain connection. daisy-chain connection to v bp of the second device or do not connect. 10 v bn negative bus voltage. 11 v cm reserved for analog devices use only. do not connect. 12 v bp positive bus voltage. 13 nc reserved for analog devices use only. v bn or do not connect. 14 nc reserved for analog devices use only. v bn or no connect 15 v sci analog signal chain input. v bn when not in use. 16 v cm reserved for analog devices use only. do not connect. dap1 v cm exposed pad: reserved for analog devices use only. do not connect. dap2 v bn exposed pad: negative bus voltage.
adxl180 rev. a | page 9 of 60 terminology full-scale range (fsr) the full-scale range of a device, also referred to as the dynamic range, is the maximum and minimum g level that reports on the output following the internal filtering. as a reference, there is usually a trade-off in increased sensitivity and resolution for decreased full-scale range, and vice versa. noise device noise is the noise content between 10 hz and 400 hz, as noted in the specifications tabl e 1 . device noise can be measured by performing an fft on the digital output and measuring the noise content between the specified frequency limits. sensitivity the sensitivity of a device is the amount of output change per input change. in this device, it is most usually referred to in units of lsb/ g . scale factor the scale factor is the amount of input change per output change. in this device, it is most usually referred to in units of g /lsb. offset offset is the low frequency component of the output signal that is not due to changes in input acceleration. slow moving effects, such as temperature changes and self-heating during start up, may affect offset, but the time scale for these effects is beyond that of a typical shock or crash event. auto-zero auto-zero is an offset compensation technique intended to reduce the long term offset drift effects of temperature and aging. this technique is designed to limit interaction with true acceleration signals. for more information, see figure 32 . rise/fall times the device rise time is defined as the amount of time necessary for the manchester encoded signal (i mod ) to transition from 10% to 90% of its final value (i sig ). device fall time is the amount of time required for the i mod signal to fall from 90% of i sig to within 10% of i idle . idle current idle current is the current of the device when at rest, waiting for a synchronization pulse, or in between current modulation. modulation current modulation current is the amount of current that the adxl180 device pulls from the bus when communicating. for more information, see figure 7 . phase a phase is a stage in the adxl180 state machine. for more information, see figure 22 . mode mode refers to the selection of the phase 2 method of device data communication. the adxl180 is configurable into four unique operating modes. crc a cyclic redundancy check (crc) is calculated from a set of data and then transmitted alongside that data. if the calculation technique is defined and known to the receiving device, the receiver can then check whether the crc bits match the data. if they do not match, a transmission error has occurred. parity parity is defined by the count of 1s in a binary string of data. if this count is even, then the data is determined to have even parity. often a bit is used, such as the cupar, in a configuration register that is defined in such a way as to establish a particular parity in the register to detect single bit changes during the life of the device. this is possible because a single bit change changes parity and a monitor circuit can detect this. similarly, a parity bit can be added in a data transmission to detect single bit errors if the parity of communication is preestablished for the transmit and receive systems.
adxl180 rev. a | page 10 of 60 theory of operation overview the adxl180 is a complete satellite system, including acceleration sensor, data filtering, digital protocol functionality, and a 2-wire, high-voltage, current-modulated bus interface communications port. acceleration sensor the adxl180 provides a fully differential sensor structure and circuit path. this device uses electrical feedback with zero force feedback. figure 4 is a simplified view of one of the differential sensor elements. each sensor includes several differential capa- citor unit cells. each cell is composed of fixed plates attached to the substrate and movable plates attached to the frame. displacement of the frame changes the differential capacitance, which the on- chip circuitry measures. complementary signals drive the fixed capacitor plates. the relative phasing between the two halves of the differential sensor is such that the displacement signal is differential between the two measurement channels. using the fully differential sensor and an antiphase clocking scheme helps reject electrical environmental noise (see figure 5 ). the adxl180 acceleration sensor uses two electrically isolated, mechanically coupled sensors to measure acceleration as shown in figure 5 . the clock phasing of the readout is such that the electrical signal due to acceleration is differential between the channels and environmental disturbances couple in as a common- mode signal. the following differential amplifier can then extract the acceleration signal while suppressing the environmental noise. electrical feedback adjusts the amplitudes of the fixed capacitor plates drive signals such that the ac signal on the moving plates is zero. the feedback signal is linearly proportional to the applied acceleration. this feedback technique ensures that there is no net electrostatic force applied to the sensor. movable frame acceleration unit self-test forcing cell unit sensing cell moving plate fixed plates plate capacitors a nchor anchor motion 07544-004 figure 4. simplified view of adxl180 sensor under acceleration amp ? v out 0 + ? emi disturbance response common to both channels acceleration response differential between channels 0 acceleration sensing axis +x-axis sensor ?x-axis sensor isolated mechanical couplings + spring 07544-005 figure 5. differential acceleration sensing
adxl180 rev. a | page 11 of 60 signal processing the adxl180 contains an on-board set of signal processing blocks both prior to and after adc conversion. the first stage is a fully differential, switched capacitor, low-pass, three-pole bessel filter. range scaling is also handled in one of the filter blocks, enabling 50 g to 500 g range capability. at this point, an analog output test signal (v sco ) is available to the user in a diagnostic mode. the signal then converts by a 10-bit rail-to-rail sar adc. in the digital section, an auto-zero routine is available to the user as part of the state machine in addition to error detection features such as offset drift detection. digital communications state machine the adxl180 digital state machine is based on a core 5 phase state machine implemented in high density cmos. this state machine handles the sequential states of phase 1. initialization. phase 2. device data transmission, including individual serial number and user-programmed data. phase 3. self-diagnostic, including automatic full electro- mechanical self-test with internal error detection available. phase 4. auto-zero initialization, if selected. during this phase, acceleration data is already available. phase 5. normal acceleration data transmission. 2-wire current modulated interface the data that is generated during these five phases is trans- mitted using a 2-wire high voltage communication port. this allows the device to be powered by a fixed supply voltage, and communicate back to the system or ecu electronics by modulating current. current modulated messages are encoded using man- chester encoding. synchronous operatio n and dual device bus in a point-to-point bus topology, the adxl180 supports asyn- chronous transmission of data to the receive device every 228 s, controlled by the on-board state machine. a synchronous option is also available, allowing two devices to be on the same bus using time division multiplexing where each device transmits its data during a known time slot. synchronization is achieved by voltage modulated synchronization pulses, configuring the adxl180 device into a synchronous mode, and establishing data frame time slots. the high voltage communication port registers valid synchronization pulses and enables message-by-message advancement of the state machine rather than asynchronous timed regular data transmission. programmed memory and configurability factory-programmed serial number and manufacturer information the adxl180 includes a 32-bit factory-programmed serial number, as shown in table 5 . this serial number transmits during phase 2 of startup for all devices to enable robust quality tracking of individual devices, and it is field readable. in addition, this data includes revision information and manufacturer identi- fication in case multiple devices used within a single application are from different manufacturers or generations of parts. user-programmable data register the adxl180 gives the user an 8-bit register of user-program- mable data, which is transmitted during phase 2 of the state machine. in addition, the ud8 bit, a ninth user-available bit, is transmitted separately during phase 2 and can be used for various purposes, such as orientation definition or module type. table 5. factory programmed and user-programmed memory programmed by configuration mode register address configuration mode register name msb d6 d5 d4 d3 d2 d1 lsb d7 d0 user 0000b ureg ud7 ud6 ud5 ud4 ud3 ud2 ud1 ud0 0001b creg0 ud8 bde md1 md0 fdly dly2 dly1 dly0 0010b creg1 sti aze syen adme erc svd dat man 0011b creg2 cuprg cupar scoe fc1 fc0 rg2 rg1 rg0 factory 1011b sn0 snb7 snb6 snb5 snb4 snb3 snb2 snb1 snb0 1100b sn1 snb15 snb14 snb13 snb12 snb11 snb10 snb9 snb8 1101b sn2 snb23 snb22 snb21 snb20 snb19 snb18 snb17 snb16 1110b sn3 snb31 snb30 snb29 snb28 snb27 snb26 snb25 snb24 1111b mfgid snprg snpar rev2 rev1 rev0 mfgid2 mfgid1 mfgid0
adxl180 rev. a | page 12 of 60 user-programmed configuration at each of these previously described points in the system, the adxl180 is highly configurable for different applications. the organization and configurable items are briefly described in this section but are covered in depth in the remainder of this data sheet. physical layer (iso layer 1) the bus interface hardware definition including the phase of manchester encoding and synchronization pulse enable/disable. data link layer (iso layer 2) the specifics of the data frame format including the data width (8-bit or 10-bit data), state vector (enable/disable), and error detection (parity or crc). application layer (iso layer 7) the serial number and configuration data transmission mode and self-test (internal self-test pass/fail discrimination or external self-test data evaluation). other signal processing related aspects of the function of the adxl180 can also be configured as follows: ? sensor scale factor (range) ? signal chain low-pass filter bandwidth ? auto-zero: enable/disable ? user-defined data in the user data register
adxl180 rev. a | page 13 of 60 physical interface application circuit a typical application circuit is shown in figure 6 . the two capa- citors shown in figure 6 are typically ceramic, x7r, multilayer smt capacitors. maximum recommended values of esr and esl are 250 m and 2 nh, respectively. capacitor tolerances of 10% are recommended. current modulation when the adxl180 device is powered on, it uses current modulation to transmit data. normally, the device pulls i idle current. when modulating, an additional current of i mod is pulled from the sensor bus. see figure 7 . adxl180 v bp v dd v bn v bp supply and configuration bus v bn c vdd 100nf c b 10nf 07544-006 figure 6. application circuit i idle t b i mod time t a 10% 50% 90% t rf 07544-007 figure 7. communication current modulation timing
adxl180 rev. a | page 14 of 60 manchester data encoding to encode data within the current modulation, the adxl180 uses manchester encoding. manchester encoding works on the principle of transitions representing binary 1s and 0s, as shown in figure 8 . manchester encoding uses a set of predefined start bits to transmit the clocking within each message, see figure 9 . the pattern of the start bits allows the receiver to synchronize itself to the bit stream. these start bits are user selectable. logic 0 logic 1 start bits i sig i idle logic 0 logic 1 bus c urrent 0 7544-008 figure 8. manchester-1, start bits and phase logic 0 logic 1 start bits i sig i idle logic 0 logic 0 0 7544-009 bus c urrent figure 9. manchester-2, bit coding table 6. man options man manchester coding start bits logic 0 logic 1 0 manchester-1 (default) 1, 0 falling edge rising edge 1 manchester-2 0, 0 rising edge falling edge the phase of the manchester encoded data can be selected via a bit in the configuration registers. see figure 8 and figure 9 for details. the configuration bit that sets the phase of the man- chester encoder also sets the value of the two start bits. the start bits are 1, 0 for manchester-1 and 0, 0 for manchester-2. for phase and start bit information, see table 6 . operation at low v bp or low v dd the adxl180 monitors its internal regulator voltage to ensure proper operation. if the bus voltage drops, or the internal regu- lator voltage drops below the v pur reset threshold, the device resets. see the voltage regulator monitor reset operation section. operation at high v dd if the regulator pin detects a high voltage, such as from a short or leakage condition, the adxl180 detects an error. see the voltage regulator monitor reset operation section for more details.
adxl180 rev. a | page 15 of 60 communications timing and bus topologies data transmission the analog data (available to the user by enabling the v sco output) is sampled every 228 s when the device is configured to run asynchronously. in synchronous operation, an adc conversion is triggered upon the detection of a valid sync pulse. in both cases, the data is held until a subsequent adc conversion is performed. this results in an additional time delay of either 228 s or one sync pulse period from the sampling of the analog data to when it is transmitted via manchester encoded data. analog-to-digital conversions are performed prior to the device entering run-time mode (phase 5) thereby ensuring that the data from the adc is never in an unknown state. this holds true upon receipt of the first sync pulse in run-time mode (phase 5). input acceleration adc conversion (38s conversion every 228s.) adxl180 return current digital waveform the data acquired during a given adc cycle is not transmitted until a subsequent data acquisition is performed. in asynchronous operation mode, this delay 228s. n ?2 n ?1 n ?3 n ?2 n ?1 n 0 n 0 n 1 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 0 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 07544-010 ? ? ? ? ? figure 10. asynchronous data transmission (timing not to scale)
adxl180 rev. a | page 16 of 60 input acceleration adc conversion ( performed after syn c pulse detection) sync pulse adxl180 return current digital waveform n ?2 n ?1 n ?3 n ?2 n ?1 n 0 n 0 n 0 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 0 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 07544-011 once a valid sync pulse is detected the device will perform an adc conversion on the (available) analog input signal. the data from the adc conversion is held until a subsequent sync pulse is transmitted to the device. ? ? ? ? ? figure 11. synchronous data transmission (timing not to scale) asynchronous communication loop current i idle i mod t m 2 t m 2 time adc sample t adc t p 1 07544-012 t p 1 1 t p = t dd during phase 2, mode 0 2 t m = t clk times the number of bits transmitted data frame data frame figure 12. asynchronous mode data transmission timing the adxl180 data transmissions in their default mode run asynchronous to the control module. in this mode, the adxl180 timing is entirely based on the internal clock of the device. after the initialization phases are complete, the adxl180 begins to transmit sensor data every 228 s. the device transmits sensor data until the supply voltage falls below the required minimum operating level. if an internal error is detected, the device trans- mits the appropriate error code until the supply voltage falls below the required minimum operating level. asynchronous single device point-to-point topology a single device is wired in the point-to-point configuration as shown in figure 13 . this configuration must be used in asynchronous mode. do not use two asynchronous devices on one bus because communications errors are very likely to occur.
adxl180 rev. a | page 17 of 60 center module v bp device 1 nc nc v bn v bn v bc 07544-013 figure 13. asynchronous point-to-point topology synchronous communication the adxl180 data transmission can be synchronized to the control module. this synchronization is accomplished by the control module generating a synchronization pulse to the adxl180. the synchronization pulse is a voltage pulse that is superimposed on the supply voltage by the center module. figure 14 shows the synchronization pulse timing. upon detecting a synchronization pulse, the adxl180 transmits its data. configuring the adxl180 for synchronous operation table 7. sync enable (syen) options syen definition 0 synchronization pulse disabled. the device transmits data every 228 s based on the internal clock of the device. data is transmitted according to an internal state machine sequence when powered on (default). 1 synchronization pulse enabled. the device requires a synchronization pulse to samp le and transmit data. data transmission is in accordance with the internal state machine of the device. the user-defined syen bit determines whether the device is used in synchronous operation or remains asynchronous. syen, as shown in table 7 , must be set to syen = 1 to enable synchronous operation. synchronization pulse detection the adxl180 uses a digital integration method to validate the synchronization pulse. the adxl180 detects the supply voltage (v bp ) rising above the level of v spt . the state of the level detection circuit controls the count direction of an up-down counter. the counter is clocked every 1 s. the counter is incremented if the adxl180 detects a level exceeding v spt . the counter is decre- mented if the adxl180 detects a level below v spnd . operation is not defined between these thresholds. if the synchronization pulse is fully below v spnd , the pulse is rejected and not detected. the counter saturates at zero. the synchronization pulse is con- sidered valid on the next clock after the counter is incremented to seven counts. the counter is gated off (blanked) after a valid synchronization pulse is detected. once the sync pulse has been recognized as valid, a command is issued to start the acceleration data analog-to-digital conversion. the adc does not run conti- nuously in synchronous mode. the synchronization pulse detector is reenabled after t b , which is an idle bit transmission following the last data frame bit (see the data frame definition section). at this point, the device is ready to receive the next sync pulse. if the application requires or uses a pulse of nonuniform shape, such as, for example, rising above v spt and subsequently toggling such that it falls below v spt one or more times before t spd , consult analog devices, inc., applications support for further information on application specific pulse recognition. note, this counter means that when an invalid length sync pulse of less than seven counts is followed less than seven counts later by a subsequent sync pulse, detection may occur when the counter is incremented further by less than seven counts by the second pulse. bus discharge enable table 8. bus discharge enable bde definition 0 bus discharge disabled (default). 1 bus discharge enabled. only active when syen = 1. the bus discharge enable (bde) bit in the configuration registers can be set to aid in the discharge of the bus voltage after a syn- chronization pulse is detected. if the bde bit is set, the adxl180 changes the bus current (i bus ) level from i idle to i sig once a valid synchronization pulse is detected. the control module then sets the voltage on the bus to the nominal operating level. the bus capacitance is discharged by the adxl180 device. the current level of i sig acts as an active pull-down current to return the v bp voltage to the nominal supply voltage. the pull-down current pulse can also be used as a handshake with the control module acting as an acknowledgement of the synchronization pulse.
adxl180 rev. a | page 18 of 60 v sp v spnd v spt t adc t adc t ps t spd t b t spd t spp t std t m 07544-014 bus voltage no detect case detect case sync detect blanking data frame data frame synch detect/ blankin g adc busy bus discharge current (if bde = 1) adxl180 return current bus discharge current (if bde = 1) data contained is from the pervious adc conversion. figure 14. synchronization pulse timing (single device)
adxl180 rev. a | page 19 of 60 synchronous single device point-to-point topology a single device is wired in the point-to-point configuration as shown in figure 15 . the standard use of this configuration is with no delay devices. it is possible to use this topology with fixed delay devices as well, such as if line noise reduction after a sync pulse transmission is desired. center module v bp device 1 nc nc v bn v bn v bc 07544-015 figure 15. single devicesynchronous communication synchronous communication modedual device the adxl180 can be used in a dual device synchronous communication mode. this mode allows a maximum of two adxl180 devices to share a single pair of wires from the control module for power and communications. this is accomplished using time division multiplexing where each device transmits its data during a known time slot. the time slot used by each device is determined by the delay time from detection of a synchronization pulse to the beginning of data transmission. the data transmission delay time is selectable in the configuration registers. the following discussion uses the convention that the first time slot is named time slot a and the second time slot is named time slot b (see figure 16 ). the two adxl180 devices can be wired in either a parallel or series mode as described in the following sections. if a synchronization pulse is not detected, no data is sent. this is true for all initiali- zation phases and normal run-time operation. note that the minimum synchronization pulse period is t spd + t dly + t m + t b
adxl180 rev. a | page 20 of 60 bus voltage v spt v bp sync detect/ blanking device 1 ad22181 return current device 1 sync detect/ blankin g ad22181 return current device 2 time device 2 device 2 bus current device 1 t dly t spd device 1 t spp t std t b t m bus discharge current t m t b time slot a time slot b t spp 07544-016 figure 16. synchronization pulse timing (dual device)
adxl180 rev. a | page 21 of 60 configuring synchronous operation delay selection as shown in table 9 , the user can select the data timing of the second device to establish the predefined data slots. this allows for the fastest possible sampling, if required, and table 9 shows the number of data frame bits the first device may transmit to ensure no overlap. to further reduce device interference from line or system circuit effects, use higher fdly amounts than the minimum. table 9. data transmission delay codes dly2 dly1 dly0 delay time (t dly ) maximum first data frame bits 0 0 0 205 s 11 0 0 1 213 s 12 0 1 0 221 s 13 0 1 1 229 s 14 1 0 0 237 s 15 1 0 1 245 s 16 1 1 0 253 s 17 1 1 1 261 s 18 fixed delay mode fixed delay mode establishes which device transmits in the second time slot. fdly requires that either (but not both) of the two devices on the bus have the fdly bit programmed to enable the data frame transmission delay time. the device with the fdly bit set is named device 2. device 2 delays its data transmission by the amount of time programmed into the configuration register via bit dly2, bit dly1, and bit dly0. after receiving a valid synchronization pulse, only device 1, without the fdly bit set, sinks i sig as an active bus pull-down current (if the bde bit is set) to return the v bp voltage to the nominal supply voltage. table 10. fixed delay mode fdly definition 0 fixed delay mode disabled (default). 1 fixed delay mode enabled. de vice transmits data in the time slot delayed by t dly as defined by dly2 to dly0. caution: do not set device 2 using time slot b as bde = 1. only device 1 should draw i sig as an active pull-down when the bde bit is set. it is good practice to never have bde = 1 and fdly = 1 in the same device. autodelay mode table 11. autodelay mode enable (adme) options adme definition 0 autodelay mode is disabled. the part does not check for a second device on the line and does not pull any extra current during startup (default). 1 autodelay mode detection is enabled. pull down i det for 6 ms at power up. the autodelay mode allows two identically configured devices to be wired in a series configuration. the two devices automatically configure the two node network upon power up. the configura- tion bit (adme) must be set to enable the autodelay mode. a device with the adme bit set sinks a bus current of i det for 6 ms upon power up. the first device in the series configuration (device 2) detects the presence of the other device in the series (device 1) by sensing the i det current passing though itself from pin v bp to pin v bc during the first 6 ms of the power-up initialization phase 1. if the current draw of device 1 is present, device 2 delays its data transmission by the amount of time programmed into the configuration register via bit dly2, bit dly1, and bit dly0. therefore, device 2 transmits its data during time slot b. the data transmission delay time of device 2 is usually selected based on the number of bits in the data frame. after receiving a valid synchronization pulse, only device 1 sinks i sig as an active pull-down current (if the bde bit is set) to return the v bp voltage to the nominal supply voltage. device 2 (using time slot b) never sinks i sig as an active pull-down even if the bde bit is set. in a single device network, the unit that would be called device 1 is not present. therefore, the single device detects no current draw through the v bc pin during the power-on initialization. in this case, the single device transmits data during time slot a. this allows a device programmed with a nonminimum delay time to be used as either device 1 or device 2 in a series configuration or as a single device. the autodelay mode detect function samples the state of the autodelay detect sense circuit every 500 s during the first 6 ms of phase 1. a total of four consecutive samples must be valid to place the device in the autodelay mode. caution: do not send an additional valid sync pulse during the blanking period, t std or t b , for either device, because it incurs the risk of the signal being misinterpreted and a change in message response timing. dual device synchronous parallel topology the two devices are wired in a parallel configuration as shown in figure 17 . this configuration must be run in the fixed delay mode. center module v bp device 1 nc nc v bn v bn v bc v bp device 2 nc nc v bn v bn v bc 07544-017 figure 17. dual deviceparallel configuration
adxl180 rev. a | page 22 of 60 center module v bp device 1 v bn v bn v bc v bp device 2 nc nc v bn v bn v bc 07544-018 dual device synchronous series topology the two devices are wired in a series configuration as shown in figure 18 . the series configuration can be configured to run in either of two modes: fixed delay or autodelay. these modes are configured using the fdly and adme bits in the configuration registers. figure 18. dual deviceseries configuration
adxl180 rev. a | page 23 of 60 data frame definition data frame transmission format data bits logic signal at control module decoder ?0? ?1? time data bits 0 0 loop current i mod i idle start bit 0 start bit 1 start bit 0 start bit 1 t m t b 07544-019 figure 19. data message timing (manchester-1, bit coding) a data frame starts with two start bits. the value of these two bits is determined by the manchester encoding mode select bit. see the manchester data encoding section. figure 19 shows the basic format and timing of the data frame. a 1-bit idle time is an implicit stop bit at the end of a data frame. data frame configuration options figure 20 diagrams the protocol data frame construction options. the data frame can be broken into four specific fields as follows: ? start bitstwo start bits are always transmitted at the start of the data frame. these bits are used to synchronize the center module decoder with the manchester encoded signal. ? error checkinga single parity bit or a 3-bit crc code can be selected. ? state vectoridentifies the type of data in the data field. it can be disabled. when it is disabled, it is not transmitted. ? datathe device data and sensor data can be transmitted in either 8-bit or 10-bit mode. depending on the settings of the configuration register bits (erc, svd, and dat), the data frame can be from 11 bits to 18 bits in length. figure 20 shows the formats of the available data frames. note that the error checking field is transmitted first when the crc is selected but transmitted last when parity is selected. see figure 20 for specific examples of full protocol configurations.
adxl180 rev. a | page 24 of 60 start bits 01012 crc 012 state vector 0 10-bit data 123456789 transmitted first 000 001 010 011 100 110 111 101 erc dat creg bit name svd start bits 0 1012 state vector 0 10-bit data p 0 123456789 start bits 01012 crc 0 10-bit data 123456789 start bits 01012 crc 0 8-bit data 1234567 start bits 01012 crc 012 state vector 0 8-bit data 1234567 start bits 010 10-bit data p 0 123456789 start bits 01012 state vector 0 8-bit data p 0 1234567 start bits 010 8-bit data p 0 1234567 07544-020 figure 20. data frame formats
adxl180 acceleration data coding rev. a | page 25 of 60 acceleration input ?fs +fs 11 1111 1111 sensor code 0 11 1111 1110 10 0000 0010 10 0000 0001 10 0000 0000 00 0000 0000 01 1111 1111 01 1111 1110 01 1111 1101 01 1111 1100 00 0000 0001 07544-021 figure 21. 10-bit adc transfer characteristic table 12. dat data bit options dat definition 0 10-bit data sensor data transmitted. 8-bit phase 2 configuration data left justified in 10-bit data frame (default). 1 8-bit sensor data transmitted. the sensor data coding is dependent on the configuration register bit settings. either 8-bit or 10-bit sensor data can be transmitted. this 8-bit or 10-bit data range is either full range or reduced range. whether the data range is full or reduced depends on the setting of the state vector disable and auto-zero enable configuration register bits. for more information, see table 13 . table 13. full and reduced sensor and device data ranges svd 1 aze 2 data range 0 0 full 0 1 reduced 1 0 reduced 3 1 1 reduced 3 1 svd is the state vector disable configuration bit. 2 aze is the auto-zero en able configuration bit. 3 a configuration error is re ported if phase 2 mode 0 is selected with the state vector disabled (svd = 1). the adxl180 transmits a configura tion error code during run time and no sensor data is transmitted. table 14. 8-bit full sensor data range coding decimal hex binary (twos complement) description +127 0x7f 0111 1111 most positive (+fs) acceleration value +126 0x7e 0111 1110 +125 0x7d 0111 1101 +1 0x01 0000 0001 0 0x00 0000 0000 zero (0) acceleration value ?1 0xff 1111 1111 ?126 0x82 1000 0010 ?127 0x81 1000 0001 ?128 0x80 1000 0000 most negative (?fs) acceleration value table 15. 10-bit full sensor data range coding decimal hex binary (twos complement) description +511 0x1ff 01 1111 1111 most positive (+fs) acceleration value +510 0x1fe 01 1111 1110 +509 0x1fd 01 1111 1101 +1 0x01 00 0000 0001 0 0x00 00 0000 0000 zero (0) acceleration value ?1 0x3ff 11 1111 1111 ?510 0x202 10 0000 0010 ?511 0x201 10 0000 0001 ?512 0x200 10 0000 0000 most negative (?fs) acceleration value table 16. 8-bit reduced sensor data range coding table 17. 10-bit reduced sensor data range coding decimal hex binary (twos complement) description +464 0x1d0 01 1101 0000 most positive (+fs) acceleration value 0 0x000 00 0000 0000 zero (0) acceleration value ?464 0x230 10 0011 0000 most negative (?fs) acceleration value decimal hex binary (twos complement) description +116 0x74 0111 0100 most positive (+fs) acceleration value 0 0x00 0000 0000 zero (0) acceleration value ?116 0x8c 1000 1100 most negative (?fs) acceleration value
adxl180 rev. a | page 26 of 60 state vector coding table 18. svd data bit options svd definition 0 state vector is enabled (default). 1 state vector is disabled, a reduced data range is used. the 3-bit state vector field contains a code that defines the meaning of the data contained in the 8- or 10-bit data field. these definitions are listed in table 19 . when selected, the 3-bit state vector is appended to the 8- or 10-bit data field and transmitted as part of the data frame. state vector descriptions table 19. state vector table sv2 sv1 sv0 state phase 1 data in frame description 0 0 0 normal operation 5 sensor data this is the running state of the adxl180. during this state, an analog-to-digital conversion is performed, and the resulting sensor data is transmitted every 228 s in asyn- chronous mode or every 250 s in synchronous mode. 0 0 1 device data 2 serial number/manufacturer id/range/user and configuration register data the data field contains seri al number and/or configura- tion data. see the adxl180 state machine section for the device data transmission specifics for each md1 to md0 selection. 0 1 0 self test 0 3 sensor data with the self-test signal unasserted the adxl180 is in sensor self-test mode. the internal sensor self-test signal is unasserted. 0 1 1 self test 1 3 sensor data with the self-test signal asserted the adxl180 is in sensor self-test mode. the internal sensor self-test signal is asserted. 1 0 0 auto-zero initialization 4 sensor data the adxl180 is in phase 4. the auto-zero function is running in the fast initialization mode. 1 0 1 otp memory data na otp memory data (configuration mode data) this state vector indicates that the data sent is from the otp memory of the adxl180. this data type is only sent when the device is in configuration mode. 1 1 0 status/error na status/error data (see table 39 ) this state is set when an in ternal error is detected by the adxl180. the data field contains the error type. see the error detection section for details. 1 1 1 reserved na reserved 1 na is not applicable.
adxl180 rev. a | page 27 of 60 transmission error detection options there are two error checking methods available: a 3-bit crc and a 1-bit parity check. these are determined by the user- selected bit erc. table 20. error check (erc) bit options erc definition 0 a 3-bit crc is included in the message. crc is calculated using the polynomial x 3 + x 1 + x 0 . (default.) 1 one parity bit is included in the message. crc is not used. it is a bit that is set such th at even parity is achieved in the transmitted message. crc encoding the adxl180 can be programmed to utilize a 3-bit crc. the polynomial used for the encoding is x 3 + x 1 + x 0 . the crc calculation is performed from msb to lsb on the entire data frame. the crc state registers are initialized to zero. therefore, when checking the result of the transmission, the final crc check state should be zero. the three crc bits are always the three least significant bits in the transmission. parity encoding the adxl180 can be programmed so that the lsb of each data transmission contains a 1-bit parity check bit. the 1-bit parity check is even parity. the parity algorithm sets the parity bit to be either a one or a zero; thus, the resulting number of ones transmitted in the data frame is always an even number.
adxl180 rev. a | page 28 of 60 application layer: communication protocol state machine table 21. adxl180 start-up sequence summary name phase 1 initialization phase 2 device data phase 3 self-test phase 4 auto-zero initialization phase 5 run time function power-on reset none sequence self-test pattern fast auto-zero slow auto- zero data type transmitted none serial number, configuration and range sensor, range, device ok or delimiter sensor sensor adxl180 state machine after power is applied and stabilized, the adxl180 follows a five-phase start-up sequence. the basic function of each phase is fixed as shown in figure 22 . the five phases and the function modes available in each phase are detailed in the following sections. v dd > v pur reset phase 1 initialization phase 2 device data phase 3 self-test phase 5 normal operation reset error state transmit error code phase 4 auto-zero initialization reset reset reset reset error error error error reset 07544-022 figure 22. adxl180 start-up sequence phase 1: power-on-reset initialization the power-on-reset initialization period is typically 100 ms long. it is the period of time from when the internal reset signal is deasserted until the beginning of phase 2. this time allows for circuit stabilization and entry into configuration mode. no data is transmitted during phase 1. no errors are reported during phase 1. additionally, until phase 1 is exited, the device does not respond to a transmitted sync pulse (see table 21 ). phase 2: device data transmission overview the device data consists of the serial number and configuration data. device data is transmitted during phase 2. this data can be transmitted in one of four configurable modes (see table 22 ). these modes are described in detail in the following sections. the parity of all otp memory blocks is continuously monitored (provided that the block has been programmed) beginning at the end of phase 2. see the parity encoding section for more details. table 22. md phase 2 device data mode select codes md1 md0 name definition 0 0 mode 0 adifx mode device data (default) 0 1 mode 1 range data only (range selection limited) 1 0 mode 2 8-bit coded device data 1 1 mode 3 10-bit coded device data during phase 2, if mode 0, mode 1, or mode 2 is selected, the device data is 8-bit data. if the 10-bit data mode is selected in combination with phase 2 mode 0, mode 1, or mode 2, the 8-bit device data is left justified in the 10-bit data field. the two lsbs are held at zero (see table 24 ).
adxl180 rev. a | page 29 of 60 influence of md on data range table 23. md settings and device data ranges mode (device data) md1 md0 svd 1 aze 2 data range 0: adifx 3 (all configuration data, serial number, and manufacturer id) 0 0 0 0 full 0 0 0 1 reduced 0 0 1 0 configuration error 0 0 1 1 configuration error 1: range data only 3 (limited range selection) 0 1 0 0 full 0 1 0 1 reduced 0 1 1 0 reduced 0 1 1 1 reduced 2: 8-bit coded device data 3 (ud[7:0], serial number, and range) 1 0 0 0 full 1 0 0 1 reduced 1 0 1 0 reduced 1 0 1 1 reduced 3: 10-bit coded device data 4 (ud[7:0], serial number, and range) 1 1 0 0 full 1 1 0 1 reduced 1 1 1 0 reduced 1 1 1 1 reduced 1 svd is the state vector disable configuration bit. 2 aze is the auto-zero en able configuration bit 3 if phase 2 mode 0, mode 1, or mode 2 is selected, the device data is 8-bit data. if the 10-bit data mode is selected in combin ation with phase 2 mode 0, mode 1, or mode 2, the 8-bit device data is left justified in the 10-bit data field. the two lsbs are held at zero (see table 24 ). 4 the 10-bit device data mode (phase 2 mode 3) is incompatible with the 8-bit data mode (the dat bit is set to 1). the device tr ansmits a configurat ion error code if phase 2 mode 3 is selected and the dat bit is set to 1. no sensor data is transmitted. device data mapping in phase 2 table 24. phase 2 device data bit ma pping in 10-bit sensor data mode db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 device data msb device data device data device data device data device data device data device data lsb 0 0 table 25. phase 2 device data bit mapping in 8-bit sensor data mode db7 db6 db5 db4 db3 db2 db1 db0 device data msb device data device data device data device data device data device data device data lsb
adxl180 rev. a | page 30 of 60 phase 2: mode description mode 0 the mode 0 option for phase 2 transmits the entire contents of the configuration registers, the serial number and the manufac- turer id byte. the total number of messages transmitted during phase 2, mode 0 is 9. asynchronous mode the device data is transmitted at a time interval of 456 s based on the internal clock of the adxl180. the 456 s period is twice the normal transmission time interval of 228 s. synchronous mode in synchronous mode, the device data is transmitted in response to the synchronization pulse generated by the control module. see the synchronization pulse detection section. transmit sn0 byte t p t p t p t p t p t p t p t p t p transmit sn1 byte transmit sn2 byte transmit sn3 byte transmit manufacturer id byte transmit ureg byte transmit creg0 byte transmit creg1 byte transmit creg2 byte ph a se 1 phase 3 phase 2 mode 0 9 t p 07544-023 figure 23. phase 2 mode 0 state machine table 26. mode 0 serial number and configuration data byte sequence byte 8 byte 7 byte 6 byte 5 byte 4 byte 3 byte 2 byte 1 byte 0 creg2 creg1 creg0 ureg manufacturer id sn3 sn2 sn1 sn0 table 27. mode 0 manufacturer id byte msb lsb snprg snpar rev2 rev1 rev0 mfgid2 mfgid1 mfgid0
adxl180 rev. a | page 31 of 60 table 28. mode 0 manufacturer id byte codes manufacturer id byte field code (binary) comments mfgid2|mfgid2|mgfid0 101b analog devices identification code rev2|rev1|rev0 000b die revision code mode 1 when phase 2 mode 1 is selected, only the range data is transmitted during phase 2. the total number of messages transmitted during phase 2 mode 1 is 480. transmit range byte phase 1 phase 2 mode 1 phase 3 479 4 80 t p 07544-024 figure 24. phase 2 mode 1 state machine a configuration error is flagged when phase 2 mode 1 is selected with a range code selection that sets a range other than one of the ranges listed in table 29 . in this case, the error state is entered immediately instead of entering phase 1. see table 39 for the error coding. when both phase 2 mode 1 and the 10-bit data mode are selected, all range data is transmitted with two zero value lsbs appended (that is, left-justified data), as shown in table 24 . note that, when mode 1 is selected with the state vector enabled and auto-zero is not enabled, the full range sensor data coding is used (see the data frame transmission format section). therefore, the positive and negative full-scale ends of the sensor data range overlap with the range and error codes. the state vector distinguishes between the types of transmitted data. the state vector identifies the range data as device data (state vector = 001b) and error codes as status/error data (state vector = 110b). normal operation sensor data has a state vector of 000b (see table 19 for details). table 29. phase 2 mode 1 range data coding 8-bit data 10-bit data state vector code description decimal hex decimal hex ?122 0x86 ?488 0x218 001b 250 g measurement range ?125 0x83 ?500 0x20c 001b 50 g measurement range ?128 0x80 ?512 0x200 001b 100 g measurement range
adxl180 rev. a | page 32 of 60 mode 2 device data when mode 2 is selected, the d evice data that is transmitted consists of the ureg byte, four configuration register bytes (see figure 26 ), and the 4-byte serial number. the data is transmitted one bit per message. each message represents either a logic 0 or a logic 1. the code, 0x7a (+122d), represents a logic 0 and the code, 0x79 (+121d), represents a logic 1 in 8-bit data mode. see table 30 for both 8-bit and 10-bit data coding. the delimiter code depends on the range setting in the configuration registers. the delimiter byte used for each range setting is listed in table 31 . the data is transmitted in the following sequence and as shown in figure 25 . the total number of messages transmitted during mode 2 phase 2 is 480. 1. transmit delimiter code 64 times. 2. transmit 32 messages of serial number data (32 bits of information, one bit per message). 3. transmit 12 messages of user bits (12 bits of information, one bit per message). see table 32 . 4. transmit delimiter code eight times. 5. repeat step 2 through step 4 seven times. user bits and user register (ureg) the user bits (u11 to u0) information transmitted during phase 2 mode 2 maps into the user and configuration register data stored in the otp memory of the adxl180. this includes the 8-bits in the ureg. the mapping is shown in table 32 . see the configuration specification section for information about the definition and function of the user and configuration registers data bits. 10-bit data and mode 2 during phase 2 when both mode 2 and the 10-bit data mode are selected, all device data messages are transmitted with two zero-value lsbs appended (that is, left-justified data). note that, when mode 2 is selected with the state vector enabled and the auto-zero is not enabled, the full range sensor data coding is used (see the data frame transmission format section). therefore, the positive and negative full-scale ends of the sensor data range overlap with the device data and status/error codes. the state vector distinguishes between the types of transmitted data. the state vector identifies the device data (state vector = 001b) and the status/error codes (state vector = 110b). normal operation sensor data has a state vector of 000b. see table 19 and table 16 . transmit delimiter code phase 1 phase 3 phase 2 mode 2 63 4 80 t p transmit sn data bit code transmit user data bit code transmit delimiter code 31 11 7 7 07544-025 figure 25. phase 2 mode 2 state machine
adxl180 rev. a | page 33 of 60 phase 2 phase 3 phase 1 st data/ status delimiter serial number/ user data serial number/ user data serial number/ user data serial number/ user data serial number/ user data serial number/ user data serial number/ user data serial number/ user data 12 31 32 34567 8 9 10 11 12 13 14 33 34 39 40 41 42 43 44 45 46 47 48 49 50 51 52 15 16 17 18 19 21 22 23 24 25 26 27 28 29 20 30 delimiter user bits lim lim lim lim lim lim lim lim sn31 sn30 sn29 sn28 sn27 sn26 sn25 sn24 sn23 sn22 sn21 sn20 sn19 sn18 sn17 sn16 sn15 sn14 sn13 sn12 sn11 sn10 sn09 sn08 sn07 sn06 sn05 sn04 sn03 sn02 sn01 sn00 serial number 35 36 37 38 u11 u10 u09 u08 u07 u06 u05 u04 u03 u02 u01 u00 de de de de de de de de 07544-026 figure 26. phase 2 mode 2 device data transmission table 30. phase 2 mode 2 sensor and device data coding 8-bit data 10-bit data data type description decimal hex decimal hex +127 0x7f +508 0x1fc undefined unused +126 0x7e +504 0x1f8 undefined unused +125 0x7d +500 0x1f4 error code device error +124 0x7c +496 0x1f0 undefined unused +123 0x7b +492 0x1ec undefined device ok +122 0x7a +488 0x1e8 logic 0 device data : logic 0 +121 0x79 +484 0x1e4 logic 1 device data : logic 1 +120 0x78 +480 0x1e0 undefined unused +119 0x77 +476 0x1dc undefined unused +118 0x76 +472 0x1d8 undefined unused +117 0x75 +468 0x1d4 undefined unused +116 0x74 +464 0x1d0 acceleration data most positive (+fs) acceleration value +115 0x73 +460 0x1cc acceleration data 0 0x00 0 0x 000 acceleration data zero (0) acceleration value ?115 0x8d ?460 0x234 acceleration data ?116 0x8c ?464 0x230 acceleration data most negative (?fs) acceleration value ?117 0x8b ?468 0x22c undefined unused ?118 0x8a ?472 0x228 undefined unused ?119 0x89 ?476 0x224 undefined unused ?120 0x88 ?480 0x220 undefined unused ?121 0x87 ?484 0x21c undefined unused ?122 0x86 ?488 0x218 status code 250 g measurement range ?123 0x85 ?492 0x214 undefined unused ?124 0x84 ?496 0x210 undefined unused ?125 0x83 ?500 0x20c status code 50 g measurement range
adxl180 rev. a | page 34 of 60 8-bit data 10-bit data data type description decimal hex decimal hex ?126 0x82 ?504 0x208 undefined unused ?127 0x81 ?508 0x204 undefined unused ?128 0x80 ?512 0x200 status code 100 g measurement range table 31. phase 2 mode 2 delimiter coding range state vector code 8-bit data 10-bit data decimal hex decimal hex 50 g 001b ?125 0x83 ?500 0x20c 100 g 001b ?128 0x80 ?512 0x200 150 g 001b ?125 0x83 ?500 0x20c 200 g 001b ?125 0x83 ?500 0x20c 250 g 001b ?122 0x86 ?488 0x218 350 g 001b ?125 0x83 ?500 0x20c 500 g 001b ?125 0x83 ?500 0x20c
adxl180 rev. a | page 35 of 60 table 32. phase 2 mode 2 user bit mapping user bit device data bit name u11 syen u10 rg2 u09 rg1 u08 rg0 u07 ud7 u06 ud6 u05 ud5 u04 ud4 u03 ud3 u02 ud2 u01 ud1 u00 ud0 mode 3 device data in phase 2 mode 3, the 10-bit data codes, ?512 (0x200) to ?481 (0x21f), are used to transmit the device data. the data coding is shown in tabl e 34 and in figure 27 . one 4-bit nybble of the device data (encoded as one of 16 nybble codes) is transmitted in each 10-bit message. the number of the data nybble is identi- fied by the preceding nybble number (nn) code as detailed in table 33 . this allows a total of (16 4) = 64 unique bits of device data to be transmitted during phase 2. each message is repeated 32 times for each nybble number. the specific meaning of each data nybble is defined in table 33 . the total number of messages transmitted during phase 2 in mode 3 is (32 16) = 512. user register (ureg) the user register ureg[7:0], in mode 3 transmit during nybble 7 (ureg[7:4]) and nybble 8 (ureg[3:0]). use with state vector enabled when mode 3 is selected with the state vector enabled and the auto-zero not enabled, the full range sensor data coding is used (see the data frame transmission format section). therefore, the positive and negative full-scale ends of the sensor data range overlap with the device data and status data codes. the state vector distinguishes between the types of transmitted data. the state vector identifies the device data (state vector = 001b) and status codes as status/error data (state vector = 110b). normal opera- tion sensor data has a state vector of 000b (see table 19 ). illegal configuration: mode 3 and 8-bit data a configuration error is flagged if phase 2 mode 3 is selected and the configuration register is programmed to select the 8-bit data mode. in this case, the error state is entered immediately instead of phase 1. see the error detection section for more information. phase 1 phase 2 phase 3 nn1 data1 nn1 data1 32 messages nn2 data2 nn2 data2 nn16 data 16 nn16 data 16 32 messages 32 messages 07544-027 figure 27. mode 3 device data transmission table 33. phase 2 mode 3 device data mapping device data nybble no. definition binary code nybble sent 1 1 protocol id 001 0011 2 number of nybbles sent 16 10000 0000 3 manufacturer analog devices 101 1010 4 sensor type accelerometer 00001 0001 5 sensor range 2 100 g 0000 0000 50 g 0001 0001 200 g 0010 0010 other 0011 0011 6 bde and rs rs = 0, bde = 0 0000 0000 rs = 0, bde = 1 0001 0001 rs = 1, bde = 0 0010 0010 rs = 1, bde = 1 0011 0011 7 user data (ud bits[7:4]) 0 to 255 xxxx 3 xxxx 8 user data (ud bits[3:0]) 0 to 255 xxxx xxxx 9 serial number (bits[31:28]) xxxx xxxx 10 serial number (bits[27:24]) xxxx xxxx
adxl180 rev. a | page 36 of 60 device data nybble no. definition binary code nybble sent 11 serial number (bits[23:20]) xxxx xxxx 12 serial number (bits[19:16]) xxxx xxxx 13 serial number (bits[15:12]) xxxx xxxx 14 serial number (bits[11:8]) xxxx xxxx 15 serial number (bits[7:4]) xxxx xxxx 16 serial number (bits[3:0]) xxxx xxxx 1 data nybble 1 is transmitted first. 2 if the configuration register settings have configured the adxl180 for a range other than 50 g , 100 g, or 200 g, the other code (0011b) is sent. in these cases, the ud bits can be used to indicate the actual range. 3 x indicates that the data is device dependent. table 34. phase 2 mode 3 sensor and device data coding decimal hex data type description 511 0x1ff undefined unused undefined unused 501 0x1f5 undefined unused 500 0x1f4 status device error 499 0x1f3 undefined unused undefined unused 488 0x1e8 undefined unused 487 0x1e7 status device ok 486 0x1e6 undefined unused undefined unused 465 0x1d1 undefined unused 464 0x1d0 acceleration data most positive (+fs) acceleration value acceleration data 0 0x000 acceleration data zero (0) acceleration value acceleration data ?464 0x230 acceleration data most negative (?fs) acceleration value ?465 0x22f undefined unused undefined unused ?480 0x220 undefined unused ?481 0x21f data nybble device data 1111 ?482 0x21e data nybble device data 1110 ?483 0x21d data nybble device data 1101 ?484 0x21c data nybble device data 1100 ?485 0x21b data nybble device data 1011 ?486 0x21a data nybble device data 1010 ?487 0x219 data nybble device data 1001 ?488 0x218 data nybble device data 1000 ?489 0x217 data nybble device data 0111 ?490 0x216 data nybble device data 0110 ?491 0x215 data nybble device data 0101 ?492 0x214 data nybble device data 0100 ?493 0x213 data nybble device data 0011 ?494 0x212 data nybble device data 0010 ?495 0x211 data nybble device data 0001 ?496 0x210 data nybble device data 0000
adxl180 rev. a | page 37 of 60 decimal hex data type description ?497 0x20f nybble number device data nybble 16 ?498 0x20e nybble number device data nybble 15 ?499 0x20d nybble number device data nybble 14 ?500 0x20c nybble number device data nybble 13 ?501 0x20b nybble number device data nybble 12 ?502 0x20a nybble number device data nybble 11 ?503 0x209 nybble number device data nybble 10 ?504 0x208 nybble number device data nybble 9 ?505 0x207 nybble number device data nybble 8 ?506 0x206 nybble number device data nybble 7 ?507 0x205 nybble number device data nybble 6 ?508 0x204 nybble number device data nybble 5 ?509 0x203 nybble number device data nybble 4 ?510 0x202 nybble number device data nybble 3 ?511 0x201 nybble number device data nybble 2 ?512 0x00 nybble number device data nybble 1 phase 3: self-test diagnostic the adxl180 has two self-test modes, internal and external. in both modes the adxl180 applies an internally generated electro- static force to the sensor, simulating an acceleration force. this force causes the sensor proof-mass to displace. this displacement is transduced by the sensor interface electronics and passed through the signal chain to the adc. when in external self-test mode, the adxl180 transmits sensor data while activating the self-test signal several times. when in internal self-test mode, the adxl180 transmits data dependent on the setting of the phase 2 mode select bits. while doing so, the adxl180 activates the self-test signal several times. it then examines the results and either continues the start-up initialization sequence or reports an error. the detailed operation of the two self-test modes is described in the following sections. concept of self-test the fixed plates in the forcing cells are normally kept at the same potential as that of the movable frame. when self-test is activated, the voltage between the fixed plates and the moving plates in the forcing cells is changed. this creates an attractive electrostatic force, which causes the frame to move toward one set of fixed plates. the entire signal channel is active; therefore, the sensor displacement causes a signal change at the output of the adc. internal and external self-test option there are two selectable modes of operation for self-test. the self-test modes are internal and external. the self-test mode is toggled by selecting or deselecting the sti configuration bit, as shown in table 35 . table 35. self test internal (sti) options sti definition 0 external self-test. user must monitor self-test data to verify proper operation. device does not monitor its own response to the self-test stimulus. (default.) 1 internal self-test. the device internally monitors self-test data to determine proper operation. external self-test the external self-test mode applies an electrostatic force to the sensor (simulating an acceleration force) and transmits the sensor data to the control module. this allows the control module to measure the subsequent change in the sensor output value. the signal path low-pass filter of the adxl180 has a slower response time than the rise time of the internal self-test control (stc) signal. therefore, the sensor data transmitted during the external self-test sequence follows the rise and fall times of the low pass filter in response to the internal stc signal. the state vector (if enabled) provides the relative timing information indicating when the internal stc signal is applied to the sensor. the stc signal activates six times during the self-test state of the adxl180 (see figure 28 ). during external self-test, an average of the zero self-test value is computed and subsequently used to provide an initial offset correction value for the auto- zero function. see the phase 4: auto-zero initialization section for more information.
adxl180 rev. a | page 38 of 60 stc phase 4 loop current i idle i mod ph a se 3 t st t stc t sti t sti t sti time t sti 07544-028 figure 28. external self-test control timing internal self-test the internal mode self-test applies an electrostatic force to the sensor (simulating an acceleration force) and measures the change in the sensor output value. a self-test cycle (t stc ) constitutes one activation and deactivation of the self-test force. a self-test cycle is considered passed if the change in the sensor output value falls within the expected minimum and maximum self-test response levels. the internal self-test (phase 3) is exited and phase 4 is entered upon completing the second of any two successful self-test cycles. a self-test cycle is considered failed if the change in the sensor output value is not within the expected levels. the self-test cycle is then repeated. the self-test cycle is run a maximum of six times. the internal self-test (phase 3) is exited and the error state entered if fewer than two of the six self-test cycles pass. once the error state is entered, the self-test error code is transmitted until the device is reset. the internal self-test sequence is as follows: 1. wait 32 consecutive adc samples. 2. average 64 consecutive adc samples (v stz1 ). 3. enable self-test voltage. 4. wait 32 consecutive adc samples. 5. average 64 consecutive adc samples (v st p). 6. disable self-test voltage. 7. wait 32 consecutive adc samples. 8. average 64 consecutive adc samples (v stz2 ). 9. compare measured values. a. compare (v stz1 ) to specified minimum and maximum offset tolerance. b. compare (v stz2 ) to specified minimum and maximum offset tolerance. c. calculate difference (v stp ) ? (v stz1 ) and compare to specified minimum and maximum difference. d. calculate the absolute difference (v stz1 ) ? (v stz2 ) and compare to the maximum value. e. if delta is less than or equal to four counts (10 bits), then the self-test is a pass. f. if delta is greater than or equal to five counts (10 bits), then the self-test is a fail. 10. if any measurements in step 9 fail to achieve the defined limits, then repeat step 1 through step 9. repeat a maximum of five times. 11. if fewer than two out of the six self-test cycles pass, an internal self-test error flag is set. the error state is then entered. the self-test error code is sent until the device is reset. 12. phase 4 is entered upon completing the second of any two successful self-test cycles. influence of md selections on transmitted self-test data table 36. phase 3 data transmitted during internal self-test md1 md0 data 0 0 device ok 0 1 range 1 0 delimiter 1 1 device ok when the internal self-test mode is selected, the type of data transmitted during phase 3 is dependent on the setting of the phase 2 mode select bits (md1 and md0). see table 36 and table 39 for the device ok code. see the phase 2: device data transmission section for specifics of the delimiter and range codes.
adxl180 rev. a | page 39 of 60 wait 32 samples average 64 samples v stz1 no yes assert self-test signal wait 32 samples average 64 samples v stp deassert self-test signal wait 32 samples average 64 samples v stz2 offset min < v stz1 < offset max offset min < v stz2 < offset max no yes enter self-test cycle 07544-029 figure 29. first half is joined to second half of st chain calculate std = v stp ? v stz1 std min < std < std max no yes calculate stz = |v stz1 ? v stz2 | stz 4 lsb* no yes enter phase 4 increment cycle count cycle count = 6 no yes set self-test fail code enter error state enter self-test cycle *10-bit lsb increment pass count pass count = 2 no yes 07544-030 figure 30. internal self-test state machine
adxl180 rev. a | page 40 of 60 phase 4: auto-zero initialization if auto-zero is not enabled, upon entering phase 4, the adxl180 immediately passes from phase 4 to phase 5. fast auto-zero mode if auto-zero is enabled, the fast auto-zero routine begins upon entering phase 4. the last offset average measurement (vstz2) of phase 3 is used as a starting value for the fast auto-zero routine. this occurs whether internal or external self-test has been selected. see the external self-test section. the auto-zero function is described in the auto-zero operation section. the adxl180 transmits the offset corrected sensor data every 228 s in asynchronous mode during phase 4. when in synchronous mode, the adxl180 transmits the offset corrected sensor data after receiving a valid synchronization pulse during phase 4. the number of sensor values sent during phase 4 is 65,535. therefore, in asynchronous mode, the phase 4 time period is nominally 15 seconds long, during which time the device fully responds to acceleration input. error reporting if an error is detected during phase 4, (for example, offset out of range, otp parity error, and so forth), the appropriate error code is set and the error state is entered. the error code is transmitted until the device is reset. see tabl e 39 for error code specifics. no acceleration data is transmitted when the adxl180 is in the error state. phase 5: normal operation if auto-zero is not enabled, upon entering phase 5, the adxl180 transmits the measured (raw) acceleration signal every 228 s (in asynchronous mode) until power down. in synchronous mode, raw data is transmitted in response to every synchronization pulse until power down. slow auto-zero if auto-zero is enabled, the slow auto-zero routine begins upon entering phase 5. the adxl180 transmits the offset corrected acceleration signal every 228 s (in asynchronous mode) until power down. in synchronous mode, offset corrected data is transmitted in response to every synchronization pulse until power down. the auto-zero function is described in the auto- zero operation section. error reporting although the auto-zero routine continually corrects for offset drift, if an error is detected during phase 5, (for example, offset out of range, otp parity error, and so forth), the appropriate error code is set and the error state is entered. the error code is transmitted until the device is reset. see tabl e 39 for error code specifics. no acceleration data is transmitted when the adxl180 is in the error state.
adxl180 rev. a | page 41 of 60 signal range and filtering transfer function overview the three-pole, low-pass bessel filter has a selectable ?3 db corner (f lp ). the corner can be set to 100 hz, 200 hz, 400 hz, or 800 hz by programming the filter corner (fc) bits in the configuration registers. in the pass band between f hp and f lp , the response of the adxl180 is flat with the nominal scale factor defined by the settings of the range (rg) bits in the configuration registers (see figure 31 ). the auto-zero function creates a first-order high-pass filter with a ?3 db corner at f lp . note that the output of this filter is slew rate limited. the auto- zero function can be disabled by setting the appropriate bit in the configuration registers. see the specifications section for more information. ?60db/decade bessel filter frequency f lp ?3db nominal s ensitivity lsb/ g +20db/decade auto-zero filter f hp 07544-031 figure 31. bode plot of adxl180 transfer function range table 37. rg[2:0] sensor range select codes rg2 rg1 rg0 range 0 0 0 50 g 0 0 1 100 g 0 1 0 250 g 0 1 1 150 g 1 0 0 200 g 1 0 1 350 g 1 1 0 500 g 1 1 1 not used the adxl180 is configurable into the g -ranges shown in table 37 . adjusting the device g -range alters the g /lsb scale factor. selecting the 50 g range offers increased data resolution of 0.125 g /lsb; however, input signals above 50 g appear clipped on the output of the device. selecting a higher g -rating decreases the resolution of data; however, it allows for a wider full-scale range of observable signals. three-pole bessel filter table 38. fc low-pass filter bandwidth frequency select codes fc1 fc0 ?3 db lp frequency 0 0 400 hz 0 1 200 hz 1 0 100 hz 1 1 800 hz by configuring the fc1 and fc0 bits as shown in table 38 , the output filter on the adxl 180 can be set. this adjusts the ?3 db frequency of the output filter to the desired bandwidth. the adxl180 low-pass filter is a third-order, low-pass bessel filter with a ?60 db per decade roll-off. see the specifications table for more information on the tolerances of the low-pass filter bandwidth. auto-zero operation the auto-zero function is enabled by setting the appropriate bit in the configuration registers, see table 44 . this function helps reduce slow offset drifts due to aging, temperature, and so forth. the acceleration signal offset is determined by passing the acceleration signal through a one-pole digital low-pass filter. the output of this filter is then slew rate limited. the slew rate limited offset value is then subtracted from the acceleration data. this forms a slew rate limited high-pass filter as shown in figure 32 . if auto-zero mode is enabled, a fast offset compensation is performed during start up of phase 4 (fast auto-zero mode). the filter output is set to the last zero reading average performed by the self-test (phase 3). the ?3 db frequency of the digital low-pass filter is approximately 0.08 hz, and the slew rate limiter output (and therefore the offset correction) is updated every 0.5 seconds. the fast update mode (phase 4) is 15 seconds long in asynchronous mode and 65,535 t ps in synchronous mode (see the phase 4: auto-zero initialization section). if auto-zero mode is enabled, an offset compensation is performed during normal operation (phase 5). this offset compensation is performed at a slower rate than during the auto-zero initialization (phase 4). the ?3 db frequency of the digital low-pass filter is approximately 0.01 hz and the slew rate limiter output (and therefore the offset correction) is updated every five seconds. the slow update mode persists until power down. see the phase 5: normal operation section. the range of the offset corrected output is reduced compared to when the auto-zero is disabled. this is the function of the limiter block in figure 32 . this range reduction is shown in table 16 and table 17 .
adxl180 rev. a | page 42 of 60 offset drift monitoring cumulative offset drift is monitored during the normal operation of the adxl180. offset drift monitoring occurs at the same rate as auto-zero but runs independent of whether auto-zero is enabled or disabled. an offset error is flagged if the offset correction exceeds the maximum specified value. the appropriate error code is sent in the next data frame transmitted to the control module (see the offset error/offset drift monitoring section). this message is sent continuously until power to the adxl180 is removed. the error status clears on the next power-on-reset. bessel lp filter 10-bit adc digital lp filter offset overrange detect limiter enable g- sensor transmission period slew rate limiter fast/slow limiter to serial port m u x a uto-zero disable 07544-032 figure 32. auto-zero signal path
adxl180 rev. a | page 43 of 60 error detection overview the adxl180 monitors its internal operation and reports errors. the error reporting codes differ depending on whether the state vector has been enabled. tabl e 39 describes the errors and the specific codes transmitted in various configurations. the state vector allows the adxl180 to report specific errors if enabled. if the state vector is not enabled, a single error code is sent regardless of the type of error. the error code is transmitted every 228 s in asynchronous mode until power down. the error code is transmitted in response to every synchronization pulse in synchronous mode until power down. parity error due to communications protocol configuration bit error as shown in table 39 , an error code is generated if the parity of the adxl180 device otp memory is incorrect. however, if this error is due to a parity error in one of the erc, svd, dat, or man bits that govern the format of the transmitted message, the error code is transmitted in an alternate data format. receive system designs that recognize repeated message transmissions, wrong data lengths, and incorrect manchester encoding help to detect more easily that an error code is being set. table 39. status/error coding error state vector enabled state vector disabled error reporting active in phases 8-bit data mode 10-bit data mode 8-bit data mode 10-bit data mode configuration error 0x7f 127d 0x1f9 505d 0x7d 125d 0x1f4 500d 2 offset error 0x7e 126d 0x1f8 504d 0x7d 125d 0x1f4 500d 5 self-test error 0x7d 125d 0x1f7 503d 0x7d 125d 0x1f4 500d 4, 5 1 otp parity error 0x7c 124d 0x1f6 502d 0x7d 125d 0x1f4 500d 4, 5 device ok 0x7b 123d 0x1e7 487d 0x7b 123d 0x1e7 487d 3 device not ok (nok) 0x7a 122d 0x1f4 500d 0x7d 125d 0x1f4 500d 3, 4, 5 1 a self-test error reported during phase 5 indicates a failure of the internal self-test circuit, not a sensor self-test error.
adxl180 rev. a | page 44 of 60 self-test error in the adxl180, self-test is automatically run during phase 3. if the internal self-test mode is selected, then the device enters into the self-test routine as detailed in figure 29 and figure 30 . the device reports a failure during phase 3 if it does not detect two successful self-test pulses. when external self-test is enabled, the device enters into the self- test routine as detailed in figure 29 and figure 30 ; however, it reports all six self-test pulses to the control module. the control module is responsible for designation of a device failure. offset error/offset drift monitoring during phase 3, an offset calculation is performed by averaging the offset value with self-test deasserted (see figure 29 for more details). if this value is outside of the datasheet specifications, then an error is reported at the start of phase 5. additionally, the adxl180 continuously monitors long term offset drift. if the long-term offset correction exceeds the maximum specified value, then an offset error is reported. this error is reported independent of whether or not the auto-zero functionality has been enabled. voltage regulator monitor reset operation the control module can reset the adxl180 by lowering the bus supply voltage to cause a power-fail reset. figure 33 shows that, for both the undervoltage and overvoltage trip thresholds, there is a nominal 120 mv hysteresis before the voltage regulator returns to within specification. no data transmission occurs while the adxl180 is in the reset state. the bus current is held at the idle level during reset. v pur v dd (nominal) reset time power ok voltage regulator output (v dd ) v hyst v ov v hyst 07544-033 figure 33. voltage regulator monitor reset functionality
adxl180 rev. a | page 45 of 60 test and diagnostic tools v sci signal chain input test pin the v sci signal chain input test pin allows the excitation of the signal chain from the input of the sensor interface circuitry (sensor amplifier) through to the output of the current mode serial port. the function of this pin becomes active after the pin input voltage exceeds the level of about 0.8 v. below this level, the adxl180 does not respond to the voltage applied to the v sci pin. above the threshold limit of 0.8 v, the voltage signal at the v sci pin is applied to the sensor interface circuitry in parallel with the sensor signal. the applied signal is zero when the input signal is equal to the common-mode potential of the sensor interface circuitry (~v dd /2 v), see figure 34 . the v sci input scaling for all ranges is typically about 640 v/ g . the scaling of the v sci input voltage to the adc code output is dependent on the range setting of the part. +600 g 0 g ?600 g ~0.8 v dd /2 ~3.2 07544-034 g equivalent v sci test pin voltage figure 34. v sci signal chain input test pin transfer function v sco analog signal chain output test pin the v sco analog signal chain output test pin provides access to the sensor signal chain analog output voltage at the output of the bessel filter. this signal is filtered and ranged as defined by the configuration register settings. it is before the digital auto- zero function in the signal chain. therefore, it is not auto- zeroed. the configuration register scoe bit must be set to 1 to enable this output. the signal output resistance is typically 50 . connect this output to a high impedance input only. table 40. scoe v sco signal chain output enable scoe definition 0 v sco output disabled. (default.) 1 v sco output enabled. analog output prior to adc conversion is present on v sco pin. connect v sco to high impedance input, or data or sensor data may be adversely affected. table 41. typical v sco sensitivity per g -range g -range sensitivity 50 g 32.8 mv/ g 100 g 16.4 mv/ g 150 g 10.8 mv/ g 200 g 8.2 mv/ g 250 g 6.56 mv/ g 350 g 4.69 mv/ g 500 g 3.28 mv/ g
adxl180 rev. a | page 46 of 60 configuration specification overview the adxl180 configuration mode allows access to the user- programmable nonvolatile configuration registers used to define the function of the device. the configuration mode is entered by writing a 16-bit configuration mode enable key code to the v bp pin during phase 1 of the adxl180 start-up sequence, which begins immediately after power is applied to the adxl180. the 16-bit configuration mode enab le key code is 0x5a5a with no start or parity bits (see figure 36 ). the configuration mode key is sent lsb first. note that the configuration mode key code is 16 bits long and the configuration mode read/write command data frames are 14 bits long. this helps avoid misinterpretation of either by the adxl180. all configuration mode data sent to the adxl180, including the configuration mode enable key code is communicated to the adxl180 via voltage modulation of the v bp pin with respect to the v bn pin. this signal uses pulse duration modula- tion to combine the clock and digital data. the clock and data are encoded as shown in figure 35 . the adxl180 acknowledges entering the configuration mode by transmitting the contents of the creg2 register. this register contains the configuration/user data programming bit (cuprg) status. this allows the users configuration/test system to deter- mine whether the adxl180 configuration otp fuse memory has been programmed without further communication. if the configuration mode is not entered within the phase 1 initializa- tion time period, the adxl180 treats the pulses on the v bp pin as synchronization pulses (in synchronous mode) or ignores them in asynchronous mode. v bp data c loc k 1 0 time v ct 1 t ib t ib t ib t ib t ib t pgo t pg1 t pg1 t pg0 0 07544-035 figure 35. configuration mode receive pulse width data and clock encoding configuration mode enable key data frame (16 bits) configuration mode key 01011010 transmitted first 01011010 0 7544-036 figure 36. configuration mode enable key code data frame time v bp i bus 16-bit config mode key code 18-bit transmit data: creg2 t tm2 t tm1 07544-037 figure 37. configuration mode entry key code sequence
adxl180 rev. a | page 47 of 60 data frame (18 bits) data address p 21021001 transmitted first start bits state vector 21076543 03 07544-038 figure 38. configuration mode transmit data frame configuration mode transmit communications protocol in configuration mode, the adxl180 transmits the configura- tion mode register data through the current mode manchester encoded serial port. the configuration mode protocol is fixed regardless of the actual settings of the configuration registers (ram or otp). the transmit communication protocol used by the adxl180 in configuration mode is ? manchester-1 data encoding ? two start bits (10b) ? 4-bit configuration mode register address field ? 8-bit configuration mode register data field ? 3-bit state vector field (101b) ? one parity bit (even) ? synchronization pulse disabled ? auto-zero disabled ? data is transmitted lsb first this is an 18-bit protocol (including the two start bits). although similar to the adifx protocol, it is different in that parity, and not crc, is used as the error checking code. this distinguishes configuration mode messages from normal operation messages. figure 38 shows the configuration mode data frame format. table 42 shows the configuration mode transmit data bit mapping. excluding the two start bits, the word is 16 bits long. data bit db15 (transmitted last) is the parity bit. the configuration mode transmit parity is even. the parity bit is set to either 1 or 0 to make the total number of 1s in the 16-bit word an even number. data bits[db14:db11] are the four configuration mode register address bits. the following eight data bits, db10 through db3, are the eight configuration mode register data bits. the next three bits, db2 through db0, are the state vector bits. in the configuration mode, the state vector is 101b. this data frame format is different from the adifx format.
adxl180 rev. a | page 48 of 60 receive data frame (14 bits) configuration mode command (receive) communications protocol the 8-bit configuration register data is passed to the adxl180 with a read/write command bit, a 4-bit configuration register address, and a parity bit as shown in figure 39 . the read/write bit is set to indicate the desired action. a 0 indicates a write operation and a 1 indicates a read operation. the parity bit is set for even parity. the parity bit should be set to 0 or 1 to make the total number of 1s in the data frame even. the data is transmitted lsb first as shown in table 42 . data address p 210 transmitted first 21076543 0 r/w 03 07544-039 figure 39. configuration mode command (receive) data frame table 42. configuration mode transmit data bit mapping db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 parity addr 3 addr 2 addr 1 addr 0 data bit 7 (msb) data bit 6 data bit 5 data bit 4 data bit 3 data bit 2 data bit 1 data bit 0 (lsb) state vector 2 state vector 1 state vector 0
adxl180 rev. a | page 49 of 60 configuration mode communications handshaking configuration mode communications uses a handshaking protocol. following the completion of a data write or data read command being written to the adxl180, a data frame is transmitted from the adxl180 through the current mode serial port. this forms a handshake acknowledgment with the test system (see figure 40 ). the source of the data (ram or otp) transmitted in the handshake data frame is dependent on whether the otp memory has been programmed. upon receiving a configuration mode data frame, if a parity error is detected, the adxl180 returns a handshake data frame with the state vector code set to the status/error state vector code (110b). the 8-bit data field and the 4-bit address field are both set to all 0s. when the test system sends a data write command, the data that was written to the addressed configuration mode register is then written to ram, read back from the ram, and transmitted to the users test/configuration system as a handshake. this provides a data integrity check for data write commands. if there is an attempt to write data to a ram register after the cuprg bit is set, the data is ignored by the adxl180 (that is, it has no affect on the device). the data returned by the adxl180 is the contents of the addressed otp fuse register. this is the same result as if a data read command had been issued. when the test/configuration system sends a data read command, the data contained in the data frame is ignored and the data that is contained in the addressed configuration mode register is sent to the test/configuration system in response. the data sent is always read from the ram registers. if the cuprg bit has not been set (that is, the otp fuses are not programmed), the ram contains the last data written to it by the configuration/ test system. when the cuprg bit is set (that is, the otp fuses are programmed) the fuse data is loaded into the ram registers (see figure 42 ). time v bp i bus t tm2 t tm1 t tm2 t tm1 07544-040 data read data write transmit data transmit data d a ta write sequence d a t a re a d sequence handshake handshake figure 40. configuration mode write data and read data sequences
adxl180 rev. a | page 50 of 60 configuration and user data registers the configuration and user data registers are the user register, ureg, and the three configuration registers, creg0, creg1, and creg2 (see table 44 ). the adxl180 can be programmed to provide a variety of signal chain characteristics and device operating modes via configuration register creg0, configu- ration register creg1, and configuration register creg2. the configuration register and user register data can be programmed into nonvolatile otp memory. in general, the creg registers hold data that alters the function of the adxl180. the data contained in the ureg has no affect on the operation of the adxl180. the ureg bits are typically used to indicate information such as module housing type and sensing axis. the adxl180 can be programmed to transmit the ureg bits as part of the device data during power-up phase 2, depending on the phase 2 mode that is selected. configuration mode exit the configuration mode is exited by writing 0x80 to address 1010b. a communication handshake is transmitted by the adxl180 after the configuration mode exit address is written. the adxl180 reenters its start-up sequence at the beginning of the initialization phase (phase 1) immediately upon exiting the configuration mode. this method does not generate a device reset. alternatively, the configuration mode can be exited by lowering the bus supply voltage to cause a power-on-reset to occur. this method generates a device reset. serial number and manufacturer identification data registers the serial number and manufacturer identification data registers can be read in configuration mode. the manufacturer identification register is fixed at the mask level. the serial number is programmed during the final manufacturing stages. the adxl180 can be configured to send this data as part of the device data transmitted during phase 2 of the power-up initialization sequence. programming the configuration and user data registers when the desired configuration and user data has been written to the ureg and creg registers, writing a 1 to the configura- tion/user data program command bit (cuprg) causes the four bytes of configuration/user data to be permanently written to the configuration/user data otp fuse memory. the otp fuses are programmed sequentially by the adxl180 without further user intervention. this takes about 12 ms (t cup in figure 41 ). the adxl180 ignores all test system read and write commands while it is programming the fuses. the adxl180 acknowledges the completion of the program- ming sequence of the configuration/user data otp memory by sending the contents of the creg2 register as described in the configuration mode transmit communications protocol section. the creg2 register contains the configuration/user data pro- gramming bit (cuprg). this allows the test/configuration system to verify that the configuration/user data programming bit has been programmed without further communication. the contents of all of the configuration and user registers should then be read to confirm that they have been programmed to the desired settings. figure 41 illustrates a sample sequence of commands to write and then program the configuration and user registers. once programmed, the otp fuse memory settings are loaded into the ram registers during the phase 1 initialization of the adxl180 start-up sequence. figure 42 shows the basic struc- ture of the configuration and user ram/otp memory structure. time v bp v dd i bus t cup 07544-041 configuration mode key sequence ureg dat a write seq dat a write seq dat a write seq dat a write seq creg0 creg1 creg2 internal configuration register otp programming sequence dat a write cm exit creg2 handshake figure 41. example configuration register otp programming sequence
adxl180 rev. a | page 51 of 60 ram otp fuse mux cuprg otp data to transmit serial port and configuration control logic from receive serial port otp program a b sel 07544-042 figure 42. configuration mode ram and otp register structure the cuprg bit is automatically programmed to the locked state (1) at the end of the configuration/user data otp fuse programming sequence. this prevents any further writes to the ureg and creg ram registers as well as disables the confi- guration/user data otp fuse programming circuitry. the read value of this bit indicates whether the configuration/user data otp memory has been programmed (that is, locked). a 1 indicates that the otp memory block has been programmed and further test system writes to either the ram or otp configuration/user data registers are ignored. otp programming conditions and considerations note that all configuration/user otp registers are programmed when the cuprg bit is set regardless of whether the registers have been written to. the otp registers can be programmed one time only. during normal operation and in configuration mode, the internal voltage regulator is operating at 4.2 v nominal. this internal voltage changes to a nominal value of 6.5 v during the time that the adxl180 is programming the configuration and user otp fuses (t cup ). the v bp supply voltage must be held at or above the minimum fuse programming value specified in the specification table for proper fuse programming. the v bp supply current is increased during fuse programming as shown in figure 41 . the configuration/test system must supply at least the value i fp as specified. the configuration and user registers are production tested for user programming at 25c. if the minimum programming voltage is not achieved, the adxl180 does not respond to subsequent communications requests because it waits for the required programming voltage. the device does not attempt to program unless the required voltage level is achieved. the users test system should include a timeout check if the device does not respond due to this sit- uation. when properly programmed, the adxl180 issues a handshake back to the command module. do not attempt to write to the configuration registers or attempt another otp programming step until this handshake has been received. configuration/user register otp parity the configuration/user data otp cu parity bit (cupar) must be programmed to provide even parity for the configuration/ user data otp memory. the cupar bit should be set to either a 1 or a 0 to make the total number of 1s in the configuration/ user data otp memory (including the value of the otp cu parity bit) an even number. the configuration/user data otp memory is defined as creg0, creg1, creg2, and ureg. the parity calculation must include the state of all register bits including all of the ud and nu bits. the cuprg bit must also be included. during normal operation, once the configuration/ user data programming bit is set, the adxl180 monitors the parity of the configuration/user data otp memory and com- pares it against the programmed value of the cu parity bit in creg2. an otp parity error is flagged if the monitored parity and the programmed parity differ. see the error detection section. configuration mode error reporting the receive communication parity error and the otp programming voltage error are the two errors reported by the adxl180 when in configuration mode. the otp parity, configuration and other normal mode (run-time) errors are suppressed in configuration mode. the state vector code is set to a state vector of 5 (101b). the 8-bit error data code is shown in table 43 . the 4-bit address field is set to 8 (1000b). table 43. configuration mode error codes error data code error description 0000 0000b configuration mode receive parity error
adxl180 rev. a | page 52 of 60 configuration register reference the following tables define the codes for each programmable field in the three configuration registers (creg0, creg1, and creg2 ). the default setting (unprogrammed state) of all bits in all configuration registers is zero. as a result, the default configura tion of the adxl180 is compatible with the adifx operation mode and communication protocol as implemented in the adxs101 satellite transmitter. table 44. configuration and user data bit map 1 , 2 configuration mode register address configuration mode register name msb d6 d5 d4 d3 d2 d1 lsb d7 d0 0000b ureg ud7 ud6 ud5 ud4 ud3 ud2 ud1 ud0 0001b creg0 ud8 bde md1 md0 fdly dly2 dly1 dly0 0010b creg1 sti aze syen adme erc svd dat man 0011b creg2 cuprg cupar scoe fc1 fc0 rg2 rg1 rg0 0100b1001b nu x x x x x x x x 1010b cmexit 1 0 0 0 0 0 0 0 1011b sn0 snb7 snb6 snb5 snb4 snb3 snb2 snb1 snb0 1100b sn1 snb15 snb14 snb13 snb12 snb11 snb10 snb9 snb8 1101b sn2 snb23 snb22 snb21 sn b20 snb19 snb18 snb17 snb16 1110b sn3 snb31 snb30 snb29 sn b28 snb27 snb26 snb25 snb24 1111b mfgid snprg snpar rev2 rev1 rev0 mfgid2 mfgid1 mfgid0 1 x is dont care. 2 nu is not used.
adxl180 rev. a | page 53 of 60 ud[7:0] user data bits the user register is for arbitrary user data. it does not have any influence on sensor operation. this data is transmitted during phase 2 of the state machine. for more information on trans- mission format and timing, in particular depending on the setting of md bits, see the adxl180 state machine section. table 45. user data bit definitions bit names definition ud0 user data bit 0. no function, data only. ud1 user data bit 1. no function, data only. ud2 user data bit 2. no function, data only. ud3 user data bit 3. no function, data only. ud4 user data bit 4. no function, data only. ud5 user data bit 5. no function, data only. ud6 user data bit 6. no function, data only. ud7 user data bit 7. no function, data only. ud8 configuration bit table 46. ud8 configuration bit ud8 definition 0 reserved, dont care (default) 1 reserved, dont care the value of the rs bit may be transmitted during phase 2, inde- pendent of ud[7:0], depending on the selection of the md bits. bde table 47. bus discharge enable bde definition 0 bus discharge disabled (default). 1 bus discharge enabled. only active when syen = 1. the bus discharge enable (bde) bit enables a discharge of the bus voltage after a synchronization pulse is detected. if the bde bit is set, the adxl180 changes the bus current (i bus ) level from i idle to i sig when a valid synchronization pulse has been detected. see the synchronous communication section for more details and timing information. scoe table 48. scoe v sco signal chain output enable scoe definition 0 v sco output disabled. (default.) 1 v sco output enabled. analog output prior to adc conversion is present on v sco pin. connect v sco to high impedance input or data or sensor data may be adversely affected. fdly table 49. fixed delay mode fdly definition 0 fixed delay mode disabled (default). 1 fixed delay mode enabled. de vice transmits data in the time slot delayed by t dly as defined by dly[2:0]. adme table 50. autodelay mode enable (adme ) options adme definition 0 autodelay mode disabled. the part does not check for a second device on the line and does not pull any extra current during startup. (default.) 1 autodelay mode detection enabled. i det pull-down for 6 ms at power-up. sti table 51. self test internal (sti) options sti definition 0 external self-test. user must monitor self-test data to verify proper operation. device does not monitor its own response to the self-test stimulus. (default.) 1 internal self-test. the device monitors its own self-test data to determine proper operation. table 52. phase 3 data transmitted when sti = 1 md1 md0 data 0 0 device ok 0 1 range 1 0 delimiter 1 1 device ok fc[1:0] table 53. fc low-pass filter ba ndwidth frequency select codes fc1 fc0 ?3 db lp frequency 0 0 400 hz 0 1 200 hz 1 0 100 hz 1 1 800 hz rg[2:0] table 54. rg[2:0] sensor range select codes rg2 rg1 rg0 range 0 0 0 50 g 0 0 1 100 g 0 1 0 250 g 0 1 1 150 g 1 0 0 200 g 1 0 1 350 g 1 1 0 500 g 1 1 1 not used
adxl180 rev. a | page 54 of 60 md[1:0] table 55. phase 2 (device data) transmission mode select codes md1 md0 name definition 0 0 mode 0 adifx mode device data 0 1 mode 1 range data only (range selection limited) 1 0 mode 2 8-bit coded device data 1 1 mode 3 10-bit coded device data table 56. phase 2 (device data) transmission mode select codes md1 md0 data 0 0 device ok 0 1 range 1 0 delimiter 1 1 device ok table 57. md settings and device data ranges with svd and aze settings (replication of table 23) mode (device data) md1 md0 svd 1 aze 2 data range 0: adifx 3 (all configuration data, serial number and manufacturer id) 0 0 0 0 full 0 0 0 1 reduced 0 0 1 0 configuration error 0 0 1 1 configuration error 1: range data only 3 (limited range selection) 0 1 0 0 full 0 1 0 1 reduced 0 1 1 0 reduced 0 1 1 1 reduced 2: 8-bit coded device data 3 (ud[7:0], serial number and range) 1 0 0 0 full 1 0 0 1 reduced 1 0 1 0 reduced 1 0 1 1 reduced 3: 10-bit coded device data 4 (ud[7:0], serial number and range) 1 1 0 0 full 1 1 0 1 reduced 1 1 1 0 reduced 1 1 1 1 reduced 1 svd is the state vector disable configuration bit. 2 aze is the auto-zero enable configuration bit. 3 if phase 2 mode 0, mode 1, or mode 2 is selected, the device data is 8-bit data. if the 10-bit data mode is selected in combin ation with phase 2 mode 0, mode 1, or mode 2, the 8-bit device data is left justified in the 10-bit data field. the two lsbs are held at zero (see table 24). 4 the 10-bit device data mode (phase 2 mode 3) is incompatible with the 8-bit data mode (the dat bit is set to 1). the device tr ansmits a configurati on error code if phase 2 mode 3 is selected and the dat bit is set to 1. no sensor data is transmitted.
adxl180 rev. a | page 55 of 60 syen table 58. sync enable (syen) options syen definition 0 synchronization pulse disabled. device transmits data according to state machine based on internal clock every 228 s when powered (default). 1 synchronization pulse enabled. the device requires a synchronization pulse to sample and transmit data according to state machine. aze table 59. aze auto zero enable aze definition 0 auto-zero function is disabled. phase 4 has no messages. device immediately moves to normal data (phase 5) after self-test (phase 3). (default.) 1 auto-zero function enabled. see auto-zero operation section for details. erc table 60. error check (erc) bit options erc definition 0 3-bit crc is included in message. calculate crc using the polynomial x 3 + x 1 + x 0 . (default.) 1 one parity bit is included in the message. crc is not used. it is a bit that is set such th at even parity is achieved in the transmitted message. dat table 61. dat data bit options dat definition 0 10-bit data sensor data transmitted. 8-bit phase 2 configuration data left-justified in 10-bit data frame (default). 1 8-bit sensor data transmitted. svd table 62. svd data bit options svd definition 0 state vector enabled (default). 1 state vector disabled, reduced data range used. cupar and cuprg table 63. device config uration bit definitions name setting definition cupar 0 data dependent setting 1 data dependent setting cuprg 0 configuration otp memory not programmed 1 configuration otp memory programmed
adxl180 rev. a | page 56 of 60 axis of sensitivity adxl180 xxxx xxxx x out = 0 g x out = 0 g adxl180 xxxx xxxx x out = 0 g earth?s surface adxl180 xxxx xxxx x out = ?1 g adxl180 xxxx xxxx x out = +1 g 07544-043 figure 43. output resp onse vs. orientation
adxl180 rev. a | page 57 of 60 branding y cl cl cl cl cl y 180z xl # p w w 07544-044 figure 44. adxl180 laser brand table 64. adxl180 branding key line text description 1 xl accelerometer 2 180z adxl180z 3 yy year code 3 ww week code 4 cl lot code 4 p country of origin (philippines)
adxl180 rev. a | page 58 of 60 outline dimensions 080408-a 1.62 1.52 1.42 1.83 1.73 1.63 3.70 3.60 3.50 3.31 3.21 3.11 5.10 5.00 sq 4.90 1.50 1.45 1.40 top view 0.05 max 0.02 nom 0.30 0.25 0.18 1.35 1.25 1.15 exposed pads (bottom view) 0.50 bsc 0.25 bsc 0.15 max 0.20 min 0.50 0.40 0.30 pin 1 indicator s eating plane p i n 1 i n d i c a t o r for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 45. 16-lead lead frame chip scale package [lfcsp_lq] 5 mm 5 mm body, thick quad (cp-16-8) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADXL180WCPZ-RL 1 ?40c to +125c 16-lead lfcsp_lq cp-16-8 1 z = rohs compliant part.
adxl180 rev. a | page 59 of 60 notes
adxl180 rev. a | page 60 of 60 notes ?2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07544-0-11/08(a)

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